only two tags range at the same time with TDMA

[justinleeyang]

hi,arnaud:

follow the blog, https://www.bitcraze.io/2016/09/flying- ... ng-system/,
we test two tags no problem, but when add the third tag, adjust the code:

#ifndef DWM1000_TDMA_SLOT
#define DWM1000_TDMA_SLOT 2 //add more tag
#endif

#define N_NODES 11

uint8_t addresses[N_NODES+1][8] = {
{0,0,0,0,0,0,0,0},
{1,0,0,0,0,0,0xcf,0xbc},
{2,0,0,0,0,0,0xcf,0xbc},
{3,0,0,0,0,0,0xcf,0xbc},
{4,0,0,0,0,0,0xcf,0xbc},
{5,0,0,0,0,0,0xcf,0xbc},
{6,0,0,0,0,0,0xcf,0xbc},
{7,0,0,0,0,0,0xcf,0xbc},
{8,0,0,0,0,0,0xcf,0xbc},
{9,0,0,0,0,0,0xcf,0xbc},
{0xA,0,0,0,0,0,0xcf,0xbc},
{0xB,0,0,0,0,0,0xcf,0xbc},
};

other code need more adjust?

for example, now the tag is tag9, tag10, tag11, when only power up any two tags range pass, but if power up three tags range fail.
Addition, I only power up three anchors, anchor1, anchor2,anchor3.

[arnaud]

Hi Justin,

Nice that TDMA is working outside of our lab .

The variable DWM1000_TDMA_SLOTS_BITS defines the number of bit allocated for the slot number. To have 3 tags you need to set it to 2 (then there is space for 4 tags, 0 to 3). The line in config.mk will then look like that (one for each tag):
CFLAGS+= -DDWM1000_ENABLE_TDMA -DDWM1000_TDMA_SLOTS_BITS=2 -DDWM1000_TDMA_SLOT=0
CFLAGS+= -DDWM1000_ENABLE_TDMA -DDWM1000_TDMA_SLOTS_BITS=2 -DDWM1000_TDMA_SLOT=1
CFLAGS+= -DDWM1000_ENABLE_TDMA -DDWM1000_TDMA_SLOTS_BITS=2 -DDWM1000_TDMA_SLOT=2

Your change in the node list is correct (we need to remove this list, the node address can be generated from the node ID ....).

/Arnaud

[justinleeyang]

hi,

Got it! Thanks! I will try more tags, then report result!
But how to understand the following code?

Code: Select all

#ifdef DWM1000_ENABLE_TDMA
+      if (current_anchor == 0) {
+        int slotId = (boardId-9)&((1<<(DWM1000_TDMA_SLOTS_BITS+1))-1);
+        uint64_t nextReceiveTime = (poll_rx.full&(~((1ULL<<(TIME_SLOTS+DWM1000_TDMA_SLOTS_BITS+1))-1))) + (slotId*(1ULL<<(TIME_SLOTS+1)));
+        nextReceiveTime += 1ULL<<(TIME_SLOTS+DWM1000_TDMA_SLOTS_BITS+1);
+        if (!synchronized) {
+          // Starts well ahead to not risk starting in the past
+          nextReceiveTime += 1ULL<<(TIME_SLOTS+DWM1000_TDMA_SLOTS_BITS+1);
+        }
+        rangingInterval.full = nextReceiveTime - poll_rx.full;
+        synchronized = true;
+      } else {
+        rangingInterval.full = 1ULL<<(TIME_SLOTS+DWM1000_TDMA_SLOTS_BITS+1);
+      }
+
+      lastRangingStart.full = poll_tx.full;
+#endif

please help do more comment! Thanks!

[arnaud]

This is very much my first try at the problem so this explains the messiness, though since it was working I pushed it anyway. I am currently working on new anchors code and have gotten a much cleaner way of implementing this TDMA algorithm so the code will be updated. Also I wanted to explain the algorithm in the blog post but I could not manage to write it in a simple enough way but I can give it a try here.

What is happening there is that I am using base-2 modulo to define time slots and time frame. So the timeslots, and number of slot per frame, are expressed in number of bits of the timer. The timeslots starts at any timer value when its amount of bits is at 0 (for example for 4 bits it will start at 0x00, 0x10, 0x20, 0x40, etc.....). The frame starts when the number of bit for slot and for number of slots is at 0. So we define the length of each slot by setting the number of timer bits. One advantage is that this calculation is simple to make for each tag independently without needing extra message from the anchors, one drawback is that the granularity we have for time slot length and number of tags is in power of 2.

The code you have copied calculates the offset from the last poll_rx to the next timeslot when we want the packet to be received by anchor 1. It is going to be used later to calculate the transmit time in the tag timer (for TDMA it is assumed that poll_rx is sampled by Anchor 1 at the same instant than poll_tx was sampled by the tag and that all timers run at the same speed).

In the new anchor code to calculate the start of a slot in the next frame would look like:

Code: Select all

uint64_t nextReceiveTime =  TDMA_CURRENT_FRAME_START(poll_rx.full);
nextReceiveTime += TDMA_FRAME_LEN + slotId * TDMA_SLOT_LEN ;

This is hopefully a bit easier to read

[justinleeyang]

hi, arnaud:

Oh, the thesis really not easy to understand, look forward to more easy method. and I try the code, get the following information:

Code: Select all

D1:    934mm,RT: 0.0011850 s,RI: 0.0168041 s
D2:   2565mm,RT: 0.0011877 s,RI: 0.0168026 s
D3:     53mm,RT: 0.0011835 s,RI: 0.0168041 s

I use three tag and three anchor, tag9, tag10, tag11, and anchor1,anchor2,anchor3, in tag, I add some log, Dx represent range distance with x anchor, RT represent range time. and RI represent range interleave time.
(1)two tag, RI about ~8ms
(2)three tag, RI about ~16ms.
so I guess:
(3)four tag, RI about ~16ms
(4)eight tag, RI about ~32ms
(6)sixteen tag, RI about ~64ms
......

do you think right?

[justinleeyang]

hi,

because now the range time only about 1.2ms, so when two tags, range interleave time about 8ms, too big, if reduce the time interleave,
how to adjust code?

[arnaud]

I am not sure to understand. In theory the current code has about 2.1ms per timeslot which is enough time to run one TWR. The size of the timeslot (in bit) is defined there: https://github.com/bitcraze/crazyflie-f ... #L132-L134

What is RT and RI in your measurements?

[justinleeyang]

hi,
RT represent tag range time wiht a anchor. and RI represent range interleave time report the following parameter:

dwTime_t rangingInterval = {.full=0}

[arnaud]

Thanks! then there seems to be a bug.

RT of 1.2ms matches my measurements for ranging time, this is where the 2.1ms per timeslot come from. But if you are seeing about 8ms frame time for 2 tag it means that the current time slot is closer to 4ms and not 2 as wanted. Now I get your previous message, sorry for being slow .

The line I pointed earlier is the one to change to reduce the timeslot time. Setting TIME_SLOTS to 26 should give 2.1ms timeslot.

[justinleeyang]

hi,
yeah, i have tryed it, right. so 26 means about 480 slots per secondes.