first of all I would like to thank you for all the great work in this brilliant project
![:-O :shock:](./images/smilies/icon_eek.gif)
Currently I have some issues get the code (lighthouse-fpga) running correctly.
My Setup:
- ice40up5k (UPduino board) as well as an ice40-HX8K dev. kit
- Several custom boards with the PBW34S and TS4231 (identical setup like on the lighthouse-4 deck HW)
- I used them in an other project and I am quite confident that they do what they are supposed to do
![:-/ :roll:](./images/smilies/icon_rolleyes.gif)
- 1x Lighthouse 2 (Channel 1)
Background:
- In the past I have mainly used VHDL for FPGAs but now as I have seen SpinalHDL
![:-O :o](./images/smilies/icon_e_surprised.gif)
What I've done so far:
For the UP5K board, I had to change the 12MHz external clock input to pin 20 on bank 1 which had the consequence that I had to change the PLL primitive from SB_PLL40_PAD to SB_PLL40_CORE.
The same is true for the HX8K board where the clock is connected to J3 on bank 3.
After flashing the code to the boards the issues on both boards are identical:
- UART Communication works (frame boundary frame is send correctly; leds can be controlled)
- Initialization of the TS4231fails even if the "configured" output of the TS4231Configurator.v block changes to '1' (screenshot of the initialization captured with a logic analyzer is attached)
- If I attach an already initialized TS4231, which is putting out valid data on its D and E pins, frames are send over UART but no matching polynominal and thus no SID and Width is found in the print_frame.py .
- I also double checked the 48MHz and 24MHz Clocks (via Clock Divider and Output pin)
Any ideas how to hunt the bug?
Best Regards and thanks again for your awesome work!